A fuse is a circuit component, which is connected in series with a transmission line, and is used to short-circuit or open-circuit the transmission line.
The fuse has been widely used in the integrated circuit. For example, two terminals of a resistor are connected in parallel with a fuse. Whether the resistance value of the circuit is increased is determined by whether the fuse is burned off or not. Therefore, the difference between the predicted value obtained from a simulation circuit and the measured value obtained from an actual circuit could be remedied, and thus the required design specification is achieved.
Additionally, in order to increase the yield rate of a semiconductor memory device such as the static random access memory (SRAM), a redundant memory array and an option circuit containing fuses were provided. After memory cells in the memory device had been manufactured and defect cells were found by testing, the option circuit uses the fuses to join the redundant memory array in and to isolate the defect cells, so as to achieve the remedy effect.
Please refer to FIG. 1A, which is a schematic diagram showing the layout of a conventional option circuit. As FIG. 1A shows, the option circuit 11 includes a voltage source node 111 coupled to a voltage source potential Vdd, a ground node 112 coupled to a ground potential GND, and a selection node 113 coupled to an output terminal Vout. When the selection node 113 is connected to the voltage source node 111, the output terminal outputs the voltage source potential Vdd. When the selection node 113 is connected to the ground node 112, the output terminal outputs the ground potential GND.
However, the aforementioned conventional layout is difficult in the fabrication process to achieve that the selection node 113 not only might be connected to the voltage source node 111 but also might be connected to the ground node 112. Generally in this situation, either modifying one layer of photomask or a fabrication process of filling code is required to solve the selection problem, but the testing time or the fabrication cost is increased.
Furthermore, please refer to FIG. 1B, which is a schematic diagram showing the layout of another conventional option circuit. As FIG. 1B shows, the option circuit 12 includes a P-channel metal-oxide-semiconductor (PMOS) field-effect transistor 121 and a fuse 122. A first terminal of the fuse 122 is coupled to a ground potential GND. A drain terminal of the PMOS field-effect transistor 121 is coupled to a voltage source potential Vdd. A gate terminal and a source terminal of the PMOS field-effect transistor 121, and a second terminal of the fuse 122 are all coupled to an output terminal, and the PMOS field-effect transistor 121 is equivalent to a resistor having a large resistance value. When the fuse 122 is in an untrimmed state, the output terminal obtains the ground potential GND through the fuse 122. When the fuse 122 is in a trimmed state, the output terminal obtains a high logical level through the PMOS field-effect transistor 121.
However, defects of the aforementioned conventional layout follow. When the fuse 122 is in the untrimmed state, a large current Io flows in the PMOS field-effect transistor 121, thereby resulting in power dissipation. When the fuse 122 is in the trimmed state, the large current Io vanishes. Therefore, the magnitude of the large current Io is related to whether the fuse 122 is trimmed, which influences the current measurement when the integrated circuit including the option circuit 12 is measured in a stable state.
In sum, the layout of a suitable option circuit should avoid modifying one layer of photomask, avoid adding the cost for the fabrication process of filling code, or avoid generating a large current. Either of the prior arts has its drawbacks and doesn't meet the required effect. Therefore, how to improve the drawbacks of the aforementioned prior arts becomes the primary motive of the present invention.